Performing two replacements in Makefile with $(VAR:.x=.y) -


in makefile, observe can use pattern $(var:.x=.y) perform replacement, can perform 2 replacements in same call?

specifically, wish modify rather long makefile written else, includes compiler flag -wa,-adhlns=$(<:.c=.lst). since have both .c , .cpp files going under hammer single set of compiler flags, i'd apply foregoing replacement both extensions. (as is, .cpp files getting overwritten.)

i've tried -wa,-adhlns=$($(<:.c=.lst):.cpp=.lst), doesn't work. aim @ possible?

you can't that, can this:

$(addsuffix .lst,$(basename $(var))

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