linux - SPI data transfer - why MOSI goes to zero half cycle before the data transfer? -


i have spi signal output spi device. wonder why data output (mosi) goes 0 half cycle before actual data written on bus? must condition spi device? if not go zero, there problem on data transfer?

i use spidev32766.1 on linux (ubuntu 12.04 - kernel 3.7.1), processor imx233

thank in advance!!

enter image description here

the slave device doesn't care happens on data line except short period (usually <1ns) either side of active clock edge (this window defined setup , hold time specifications interface).

i have no idea why system put out "wiggle" though!


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