declaration - Verilog - individual output arrays -

this first time on stackoverflow.com , new verilog coding. may use terms incorrectly if please correct me can clearer in future posts.

i using altera fpga board there 7 ledg lights can triggered on , off. project making bcd adder ledg [7] turns on when bcd value not 0 - 9. however, don't want declare outputs [6:4]. ledg[3:0] displays binary equivalent of summation of 2 inputs.

i thought use 2 separate declaration statements tells me ledg declared is. tried combine using brackets complained that. there way simplify code. below examples of i've tried.

example 1:

module bcd (..., ledg, ...); output reg [3:0] ledg; output reg [7] ledg; endmodule 

example 2:

module bcd (..., ledg, ...); output reg ({[3:0], [7]} ledg); endmodule 

any appreciated! in advance. :-)

what you're trying not possible, if you're going output bus must specify single contiguous range.

you should declare output reg [7:0] if need output [7] , [3:0].

you can leave unused bits undriven, or if gives synthesis warning/error tie them off 0 or 1 if don't care value (ledg[6:4] = 3'b0).